Building SIC-1 in VCB Part 1: RAM

 So i've started a (hopefully) short, and fun side-project again.

I'm going to try to emulate the SIC-1 CPU within Virtual circuit board.

The SIC-1 CPU is an 8 bit CPU with 256 bytes of addressable RAM

i just realized i'm currently making it 256 bits but i'll fix that later (incorrect, turns out i was working on 8*8 bytes)

And a single instruction: SUBLEQ A, B, [C]

it's a Single Instruction Computer that should be relatively simple to emulate.

As an added challenge, however, i'm also limited to using a Universal gate to do so, 

A universal gate, then, is able to "emulate" other gates, these are the NAND and NOR gates.

I've chosen to use the NAND gate, Here's a comparison with their "standard" gates

I then added some more designs that might come in handy, a pulse-former seemed useful, and i needed some way to delay signals, an R/S latch also seemed like it'd be needed for RAM, and i also added in a D-flip flop and a manual clock circuit for testing, though i've had to use a builtin "buffer" gate here because the NAND gate delay actually delays by 2 ticks, and the latches start out in a hysteresis state where they rapidly flicker on and off, so i needed a way to keep the R connection held for 2 subsequent ticks, something i couldn't figure out how to do without manual intervention or other unwanted behavior, it seems a lot of the RS latch designs i've found assume the inputs are on by default, and they function based on the downward edge of the signal, which isn't how i'm trying to make this work (i'd like on to mean on, not off)

Then i went on to a minimal demo on how to address a specific RAM address, though i thought it had some issues, like resetting the whole word when the clock was sent. but that turned out to actually be a much better description of how RAM works

And after some tweaking and expanding to 8 addresses, i can now also read data from this RAM bus, 

Though it is a destructive read, so i'll need to think of a way to write the output back again at some point

i'll eventually also need an 8-bit demuxer which will leave me with a full 256 bytes of RAM that are neatly readable and writable using an 8-bit address


Popular posts from this blog

On the intricacies of affordance-based interfaces in C++

Building SIC-1 in VCB Part 3: Fadder and auto-RAM