Building SIC-1 in VCB Part 3: Fadder and auto-RAM

 Last time i finished the RAM, an early design for registers and did some initial trial and error with reading data from RAM via registers

Next i began some early ALU work, starting from the "traditional" full-adder i made a while back

I translated it into a NAND-only version, 

which, after some compression, ended up being the exact same size as the original so i could easily hook it into the same test rig

Then i started working on automating the RAM read/write cycle, so i could write with registers G/H and read with F/H (H will become the program counter register)

This process was somewhat painful since the RAM read signal is just barely long enough to fully store the data, so the write line has to be active before the data arrives, but stop on the same tick that the data line turns off so there's still some leftover wiring from when i tried to have it re-write its own data (which doesn't work since hysteresis can't easily set its own data when the circuit turns off)
Next up? CPU features, swapping registers, addition, negation, that sort of thing


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