Building SIC-1 in VCB Part 4: Multiplexing clock

 So, last time we built the RAM timing and full-adders, this time i found another important part that we're still missing

The Multiplexer, or MUX,

This circuit is sort of the opposite of the demuxer, where instead of turning an address into a selection of a RAM bank, we can switch between two signals.



As you can see, the circuit has some very nice stacking behavior for the switching input (in blue) which lets us switch between a number of signals (selected in red) with just one input

Of course we can also switch between multiple sets of input in a similar way to how we did with the demuxer, though here we get a rapidly shrinking set of data, and lots of inputs

Of course, this way of looking at it is somewhat abstract, but it forms the basis for something i think most of us are familiar with


but more generally, it allows us to "program" a sequence of outputs if instead of manually changing the selection pins, we attach this to a clock with a small counter circuit,

Perhaps a program somewhat like

  • increment H (program counter)
  • read H into G
  • Swap G with A
  • Copy H to D
  • increment H
  • read H into G
  • Swap G with B
  • increment H
  • read H into G
  • Swap G with C
  • E = B - A
  • Write E into D
  • if E <= 0
  • Copy C to H
i'm sure this is highly inefficient but i'll look into optimizing it once i have this working, it's a "safe" implementation.

Of course, then i had to start looking into making a clock/counter.
figured i might have to use some builtin latches for this type of pulse delay partly because i was struggling to build a proper toggle flip-flop, or at least seemingly needing an already functioning clock to get it to work properly (can't build a clock if you need a clock to do so)
i did end up using a DFF, which i showed in part 1, as a source for the clock signal, the builtin latch here sort of also acts as a power button for the computer, 
So, from left to right we start with the power button, 
then the DFF, looped back into itself to act like a toggle.
then a delay circuit, to make the hysteresis in the DFF look like a constant signal
and then 4 builtin T-flip flops because you can't feasibly get the hysteresis out of the later components, even that first one sometimes just won't start because the hysteresis doesn't stop if you flip the switch on the wrong "phase".
And finally, we have the pulse generator in order to make our clock cycle a pulse, instead of a long signal, since a long signal might screw with the timing-sensitive choreography of the RAM read/write system, which currently runs on that same 2-cycle pulse.

Next up, clearing out some space, and designing our program's inputs, outputs and the different operations i'll need to be able to perform within the CPU

Comments

Post a Comment

Popular posts from this blog

Building SIC-1 in VCB Part 1: RAM

Image
 So i've started a (hopefully) short, and fun side-project again. I'm going to try to emulate the SIC-1 CPU within Virtual circuit board. The SIC-1 CPU is an 8 bit CPU with 256 bytes of addressable RAM i just realized i'm currently making it 256 bits but i'll fix that later (incorrect, turns out i was working on 8*8 bytes) And a single instruction: SUBLEQ A, B, [C] it's a S ingle I nstruction C omputer that should be relatively simple to emulate. As an added challenge, however, i'm also limited to using a Universal gate  to do so,  A universal gate, then, is able to "emulate" other gates, these are the NAND and NOR gates. I've chosen to use the NAND gate, Here's a comparison with their "standard" gates I then added some more designs that might come in handy, a pulse-former seemed useful, and i needed some way to delay signals, an R/S latch also seemed like it'd be needed for RAM, and i also added in a D-flip flop and a manual cloc...
Read more

On the intricacies of affordance-based interfaces in C++

Image
Well that's a rather obscure title, isn't it, and it'll require some explanation about some non-standard C++ structures i've been building at work. First, i've done a little bit of work in the GO programming language, and i really enjoyed the mechanics of it's non-inheriting interface polymorphism (i've called them affordance-based interfaces) Next, i found this talk explaining how to do type erasure in C++ in order to essentially emulate these affordance-based interfaces: I wrote a prototype of this system such that i could make a set of affordance classes that describe a specific member function, and might serve as a "delegate" for that function, and an interface class that could combine several of these affordance classes into a single type-erasing interface. This part actually uses a bit of "regular" polymorphism to attain it's goal, but since i've written macros that generate all the required code for you, you can effec...
Read more

Building SIC-1 in VCB Part 3: Fadder and auto-RAM

Image
 Last time i finished the RAM, an early design for registers and did some initial trial and error with reading data from RAM via registers Next i began some early ALU work, starting from the "traditional" full-adder i made a while back I translated it into a NAND-only version,  which, after some compression, ended up being the exact same size as the original so i could easily hook it into the same test rig Then i started working on automating the RAM read/write cycle, so i could write with registers G/H and read with F/H (H will become the program counter register) This process was somewhat painful since the RAM read signal is just barely long enough to fully store the data, so the write line has to be active before the data arrives, but stop on the same tick that the data line turns off so there's still some leftover wiring from when i tried to have it re-write its own data (which doesn't work since hysteresis can't easily set its own data when the circuit turns ...
Read more